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19-4595; Rev 1; 7/09
Multiprotocol, Pin-Selectable Data Interface Chipset
General Description
The MAX13171E along with the MAX13173E/ MAX13175E, form a complete pin-selectable data terminal equipment (DTE) or data communication equipment (DCE) interface port that support the V.28 (RS-232), V.10/V.11 (RS-449/V.36, RS-530, RS-530A, X.21), and V.35 protocols. The MAX13171E transceivers carry the high-speed clock and data signals, while the MAX13173E transceivers carry the control signals. The MAX13171E can be terminated by the MAX13175E pin-selectable resistor termination network. The MAX13175E contains six pin-selectable, multiprotocol cable termination networks. The MAX13171E/MAX13173E have an internal charge pump and low-dropout transmitter output stages that allow V.10-, V.11-, V.28-, and V.35-compliant operation from a single supply. The MAX13171E/MAX13173E feature a no-cable mode that reduces supply current and disables all transmitter and receiver outputs (high impedance). Short-circuit current limiting and thermal shutdown circuitry protects the receiver and transmitter outputs against excessive power dissipation. The MAX13171E/ MAX13173E have extended ESD protection for all the transmitter outputs and receivers inputs. The MAX13171E/MAX13173E/MAX13175E operate over the +3.135V to +5.5V supply range and are available in 5mm x 7mm, 38-pin TQFN packages. These devices operate over the -40C to +85C extended temperature range.
Features
Supports V.28 (RS-232), V.10 (RS-423), V.11 (RS-449/V.36, RS-530, RS-530A, X.21) and V.35 Protocols Pin-Selectable Cable Termination Using the MAX13175E Pin-Selectable DCE/DTE Configurations 20/40Mbps (max) Data Rate in RS-449, RS-530, RS-530A, X.21, and V.35 True Fail-Safe Receivers while Maintaining V.11 and V.35 Compatibility Operates Over a Wide +3.135V to +5.5V VCC Supply Range Flexible VL Logic Reference Input Allows Interfacing Down to 1.62V Extended ESD Protection for All the Transmitter Outputs and Receivers Inputs to GND Small, 5mm x 7mm, 38-Pin TQFN Package
MAX13171E/MAX13173E/MAX13175E
Ordering Information
PART MAX13171EETU+ MAX13173EETU+ TEMP RANGE -40C to +85C -40C to +85C PINPACKAGE 38 TQFN-EP* 38 TQFN-EP*
Applications
Data Networking PCI Cards CSU and DSU Telecommunication Equipment Data Routers Data Switches
MAX13175EETU+ -40C to +85C 38 TQFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad.
Typical Operating Circuit
LL CTS DSR DCD DTR RTS RXD RXC TXC SCTE TXD
T4
R4
R3
R2
R1
MAX13173E T3
T2
T1
R3
R2
R1
MAX13171E T3
T2
T1
MAX13175E
18 LL A (141)
13 5 10 8 CTS A (106) CTS B DSR A (109) DSR B
22 6 DCD A (107) DCD B
23 20 19 4 DTR A (108) DTR B RTS A (105) RTS B
1
7
16 3 RXD A (104) RXD B
9 17 RXC A (115) RXC B
12 15 11 24 14 2 TXC A (114) TXC B SCTE A (113) SCTE B TXD A (103) TXD B
DB-25 CONNECTOR
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
SG (102) SHIELD (101)
1
Multiprotocol, Pin-Selectable Data Interface Chipset MAX13171E/MAX13173E/MAX13175E
ABSOLUTE MAXIMUM RATINGS
(All voltages to GND, unless otherwise noted.) Supply Voltages VCC ........................................................................ -0.3V to +6V VL ........................................................................... -0.3V to +6V VEE ..................................................................... +0.3V to -7.1V VDD .................................................................... -0.3V to +7.1V VDD to VCC ............................................................-0.3V to +6V Logic-Input Voltages M0, M1, M2, DCE/DTE, LATCH, INVERT, T_IN ..... -0.3V to +6V Termination Network Inputs R_A, R_B, R_C.......................................................-15V to +15V R_A to R_B (only for high-Z state) .....................................14V R_A to R_B...........................................................................6V R_A to R_C (only for high-Z state) .....................................14V R_A to R_C...........................................................................3V R_B to R_C (only for high-Z state) .......................................3V Logic-Output Voltages R_OUT ........................................................-0.3V to (VL + 0.3V) Transmitter Outputs T_OUT_, T_OUT_/R_IN_ (no-cable, V.28, V.10 modes) ...............................-15V to +15V Short-Circuit Duration to GND..................................Continuous Receiver Inputs R_IN_, T_OUT_/R_IN ............................................-15V to +15V R_INA to R_INB, T3OUTA/R3INA to T3OUTB/R3INB ................................................-15V to +15V Continuous Power Dissipation (TA = +70C) 38-Pin TQFN (derate 35.7mW/C above +70C) ........2857mW Junction-to-Case Thermal Resistance (JC) (Note 1) 38-Pin TQFN ....................................................................1C/W Junction-to-Ambient Thermal Resistance (JA) (Note 1) 38-Pin TQFN ..................................................................28C/W Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range ............................-65C to +150C Lead Temperature (soldering, 10s) ................................+300C
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to http://www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
MAX13171E ELECTRICAL CHARACTERISTICS
(VCC = +3.135V to +5.5V, VL = +1.62V to +5.5V, C1 = C2 = 1F, C3 = C4 = C5 = 4.7F (Figure 15), TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, VL = +1.8V, TA = +25C.) (Note 2)
PARAMETER VCC Operating Range VL Operating Range VL Supply Current SYMBOL VCC VL IL All inputs connected to GND, all receiver outputs low, VL = +5.5V RS-530, RS-530A, X.21, V.36/RS-449 mode (V.11), no load RS-530, RS-530A, X.21, V.36/RS-449 mode (V.11), full load ICC V.35 mode, no load V.35 mode, full load V.28 mode, no load V.28 mode, full load No-cable mode Internal Power Dissipation (DCE Mode)(Static) RS-530, RS-530A, X.21, V.36/RS-449 mode (V.11), full load PD V.35 mode, full load V.28 mode, full load CONDITIONS MIN 3.135 1.62 550 15 150 21 150 15 28 0.01 100 500 70 mW TYP MAX 5.5 VCC 800 28 200 38 210 30 42 10 UNITS V V A mA mA mA mA mA mA A
VCC Supply Current (DCE Mode) (Digital Inputs = GND or VCC) (Transmitter Outputs Static)
2
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Multiprotocol, Pin-Selectable Data Interface Chipset
MAX13171E ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.135V to +5.5V, VL = +1.62V to +5.5V, C1 = C2 = 1F, C3 = C4 = C5 = 4.7F (Figure 15), TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, VL = +1.8V, TA = +25C.) (Note 2)
PARAMETER SYMBOL CONDITIONS V.28, V.35 modes, no load (Note 3) V.28 mode, full load (Note 3) Positive Charge-Pump Output Voltage VDD V.35 mode, full load (Note 3) RS-530, RS-530A, X.21, V.36/RS-449 mode (V.11) (Note 3) No-cable mode V.28, V.35 modes, no load (Note 3) V.28 mode, full load (Note 3) Negative Charge-Pump Output Voltage VEE V.35 mode, full load, Note 3 RS-530, RS-530A, X.21, V.36/RS-449 mode (V.11) (Note 3) No-cable mode Charge-Pump Enable Time Thermal Shutdown Protection Input High Voltage Input Low Voltage Logic-Input Current Pullup Resistor Output High Voltage Output Low Voltage Output Pullup Resistor V.11 TRANSMITTER Open-Circuit Differential Output Voltage Loaded Differential Output Voltage Change in Magnitude of Output Differential Voltage Common-Mode Output Voltage Change in Magnitude of Common-Mode Output Voltage Short-Circuit Current Rise Time Fall Time VODO Open circuit, R = 1.95k, Figure 1 R = 50, Figure 1 R = 50, Figure 1 |VOD| VOC |VOC| ISC tr tf R = 50, Figure 1 R = 50, Figure 1 R = 50, Figure 1 (Note 3) VOUT = GND Figures 2, 6 Figures 2, 6 4.5 6.5 -VCC 0.5 x VODO I2I 0.2 3.0 0.2 150 V V V mA ns ns +VCC V THSD VIH VIL IIN RPUIN VOH VOL RPUY T1IN, T2IN, T3IN M0, M1, M2, DCE/DTE to VL ISOURCE = 4mA ISINK = 4mA No-cable mode (to VL) 71.4 -1 50 0.66 x VL 0.33 x VL 100 0.66 x VL 0.33 x VL +1 170 Time until all VDD and VEE specifications meet -4.84 5.6 4.6 4.9 MIN TYP 5.93 5.86 5.1 5.26 VCC -5.89 -5.74 -4.46 -4.47 0 <1 +145 ms C V V A k V V k -5.4 -3.8 -4.16 V 5.7 V MAX 7.1 UNITS
MAX13171E/MAX13173E/MAX13175E
LOGIC INPUTS (M0, M1, M2, DCE/DTE, T1IN, T2IN, T3IN)
LOGIC OUTPUTS (R1OUT, R2OUT, R3OUT)
VODL
V
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Multiprotocol, Pin-Selectable Data Interface Chipset MAX13171E/MAX13173E/MAX13175E
MAX13171E ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.135V to +5.5V, VL = +1.62V to +5.5V, C1 = C2 = 1F, C3 = C4 = C5 = 4.7F (Figure 15), TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, VL = +1.8V, TA = +25C.) (Note 2)
PARAMETER Transmitter Input to Output Propagation Delay (Figures 2, 6) Data Skew Channel-to-Channel Skew V.11 RECEIVER Differential Threshold Voltage Input Hysteresis Receiver Input Current Receiver Input Resistance Rise or Fall Time Receiver Input to Output Delay Data Skew Channel-to-Channel Skew V.35 TRANSMITTER Differential Output Voltage Output High Current Output Low Current Output Leakage Current Rise or Fall Time Transmitter Input to Output Delay Data Skew Channel-to-Channel Skew V.35 RECEIVER Differential Threshold Voltage Input Hysteresis Receiver Input Current Receiver Input Resistance Rise or Fall Time Receiver Input to Output Delay Data Skew Channel-to-Channel Skew V.28 TRANSMITTER Output-Voltage Swing Short-Circuit Current |VOD| IOH Open circuit RL = 3k 5 6 85 7.1 V mA VTH VTH IIN RIN tr, tf tPHL, tPLH |tPHL- tPLH| tSKEWR -2V VCM +2V -2V VCM +2V -10V VA,B +10V -10V VA,B +10V Figures 3, 7 Figures 3, 7 Figures 3, 7 (Note 3) Figures 3, 7 (Notes 3, 4) -0.66 15 30 3 25 3 3 -200 15 +0.66 -50 mV mV mA k ns ns ns ns VOD IOH IOL IZ tr, tf tPLH, tPHL |tPLH - tPHL| tSKEWR Full load, -4V < VCM < +4V, Figure 3 VA,B = 0V VA,B = 0V -0.25V VOUT +0.25V, power off or no-cable mode Figures 3, 6 Figures 3, 6 Figures 3, 6 (Note 3) Figures 3, 6 (Notes 3, 4) 0.44 -13 9 0.55 -11 11 0.05 5 19 35 3 3 0.66 -9 13 5 V mA mA A ns ns ns ns VTH VTH IIN RIN tr, tf tPHL, tPLH |tPHL-tPLH| tSKEWR -7V VCM +7V -7V VCM +7V -10V VA,B +10V -10V VA,B +10V Figures 2, 7 Figures 2, 7 Figures 2, 7 (Note 3) Figures 2, 7 (Notes 3, 4) -0.66 15 30 3 2.5 3 3 -200 15 +0.66 -50 mV mV mA k ns ns ns ns SYMBOL tPHL, tPLH |tPHL-tPLH| tSKEW Figures 2, 6 VL +3V, Figures 2, 6 Figures 2, 6 (Note 3) Figures 2, 6 (Notes 3, 4) CONDITIONS MIN TYP 22 20 MAX 28 25 2 3 UNITS ns ns ns
4
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Multiprotocol, Pin-Selectable Data Interface Chipset
MAX13171E ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.135V to +5.5V, VL = +1.62V to +5.5V, C1 = C2 = 1F, C3 = C4 = C5 = 4.7F (Figure 15), TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, VL = +1.8V, TA = +25C.) (Note 2)
PARAMETER Output Leakage Current Output Slew Rate Transmitter Input to Output Delay V.28 RECEIVER Input Threshold Low Input Threshold High Input Hysteresis Input Resistance Rise or Fall Time Receiver Input to Output Delay ESD PROTECTION Human Body Model T_OUT, T3OUT_/R1IN_, R_IN to GND Air Gap Discharge IEC 61000-4-2 Contact Discharge IEC 61000-4-2 15 12 8 kV VIL VIH VHYST RIN tr, tf tPHL, tPLH -15V VIN +15V Figures 5, 11 Figures 5, 11 3 0.8 1.2 1.2 0.25 5 3 150 7 2 V V V k ns ns SYMBOL IZ SRR/F tPHL, tPLH CONDITIONS -0.25V VOUT +0.25V, power off or no-cable mode RL = 3k, CL = 2500pF (swing in 3V), Figures 4, 10 RL = 3k, CL = 2500pF, Figures 4, 10 4 1 MIN TYP 0.05 MAX 5 30 2 UNITS A V/s s
MAX13171E/MAX13173E/MAX13175E
MAX13173E ELECTRICAL CHARACTERISTICS
(VCC = +3.135V to +5.5V, VL = +1.62V to +5.5V, C1 = C2 = 1F, C3 = C4 = C5 = 4.7F (Figure 15), TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, VL = +1.8V, TA = +25C.) (Note 2)
PARAMETER VCC Operating Range VL Operating Range VL Supply Current SYMBOL VCC VL IL All inputs connected to GND, all receiver outputs low, VL = +5.5V RS-530A, no load RS-530, X.21, V.36/RS-449, DCE mode, INVERT = low, full load, transmitter outputs static, digital inputs = GND or VL V.28 mode, no load V.28 mode, full load No-cable mode Internal Power Dissipation PD RS-530, X.21, V.36/RS-449; DCE mode, INVERT = low, full load V.28 mode, no load (Note 3) V.28 mode with full load (Note 3) Positive Charge-Pump Output Voltage VDD RS-530 mode, full load (Note 3) RS-530A mode, full load No-cable mode 5.6 4.84 CONDITIONS MIN 3.135 1.62 680 11 41 21 42 0.01 120 5.9 5.79 5.15 5.15 VCC 5.5 V 7.1 TYP MAX 5.5 VCC 1100 21 210 38 65 10 UNITS V V A mA mA mA mA A mW
VCC Supply Current
ICC
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Multiprotocol, Pin-Selectable Data Interface Chipset MAX13171E/MAX13173E/MAX13175E
MAX13173E ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.135V to +5.5V, VL = +1.62V to +5.5V, C1 = C2 = 1F, C3 = C4 = C5 = 4.7F (Figure 15), TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, VL = +1.8V, TA = +25C.) (Note 2)
PARAMETER SYMBOL CONDITIONS V.28 mode, no load (Note 3) V.28 mode with full load (Note 3) Negative Charge-Pump Output Voltage VEE RS-530 mode, full load (Note 3) RS-530A mode, full load No-cable mode Thermal Shutdown Protection Charge-Pump Enable Time THSD Time until all VDD and VEE specifications meet VIH VIL IIN RPUIN VOH VOL RPUY T1IN, T2IN, T3IN, T4IN M0, M1, M2, DCE/DTE, INVERT to VL ISOURCE = 4mA ISINK = 4mA No-cable mode (to VL) 71.4 -1 50 0.66 x VL 0.33 x VL 100 0.66 x VL 0.33 x VL +1 170 -4.71 MIN TYP -5.83 -5.55 -4.44 -4.44 0 +145 <1 C ms -5.3 -4.17 V MAX UNITS
LOGIC INPUTS (M0, M1, M2, DCE/DTE, INVERT, T1IN, T2IN, T3IN, T4IN, T5IN/R5OUT) Input High Voltage Input Low Voltage Logic-Input Current Pullup Resistor Output High Voltage Output Low Voltage Output Pullup Resistor V.11 TRANSMITTER (T1, T2, T3) Open-Circuit Differential Output Voltage Loaded Differential Output Voltage Change in Magnitude of Output Differential Voltage Common-Mode Output Voltage Change in Magnitude of Common-Mode Output Voltage Short-Circuit Current Output Leakage Current Rise Time Fall Time Transmitter Input to Output Prop Delay Data Skew Channel-to-Channel Skew VODO Open circuit, R = 1.95k, Figure 1 R = 50, Figure 1 VODL R = 50, Figure 1 |VOD| VOC |VOC| ISC IZ tr tf tPHL, tPLH |tPHL- tPLH| tSKEW R = 50, Figure 1 R = 50, Figure 1 R = 50, Figure 1 (Note 3) VOUT = GND -0.25V VOUT +0.25V, power-off or nocable mode Figures 2, 6 Figures 2, 6 Figures 2, 6 Figures 2, 6, VL +3V Figures 2, 6 (Note 3) Figures 2, 6 (Notes 3, 4) 0.05 4 6 20 -VCC 0.5 x VODO |2| 0.2 3.0 0.2 150 5 10 10 28 25 2 3 V V V mA A ns ns ns ns ns ns +VCC V V V A k V V k
LOGIC OUTPUTS (R1OUT, R2OUT, R3OUT, R4OUT, T5IN/R5OUT)
V
6
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Multiprotocol, Pin-Selectable Data Interface Chipset
MAX13173E ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.135V to +5.5V, VL = +1.62V to +5.5V, C1 = C2 = 1F, C3 = C4 = C5 = 4.7F (Figure 15), TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, VL = +1.8V, TA = +25C.) (Note 2)
PARAMETER V.11 RECEIVER (R1, R2, R3) Differential Threshold Voltage Input Hysteresis Receiver Input Current Receiver Input Resistance Rise or Fall Time Receiver Input to Output Delay Data Skew Channel-to-Channel Skew V.10 TRANSMITTER (T2, T4, T5) Open-Circuit Output Voltage Swing VO RL = 3.9k (out high) RL = 3.9k (out low) RL = 450 (out high) Output-Voltage Swing VT RL = 450 (out low) RL = 450 Short-Circuit Current Output Leakage Current Rise or Fall Time Transmitter Input to Output Delay V.10 RECEIVER (R2, R4, R5) Input Threshold Voltage Input Hysteresis Receiver Input Current Receiver Input Resistance Rise or Fall Time Receiver Input to Output Delay Data Skew VTH VTH IIN RIN tr, tf tPLH tPHL |tPHL - tPLH| -10V VA +10V -10V VA +10V Figures 5, 9 Figure 9 Figure 9 Figures 5, 9 (Note 3) Open circuit RL = 3k -0.25V VOUT +0.25V, power-off or no-cable mode 5 6 90 0.05 5 -0.66 15 30 3 55 109 60 7.1 50 25 +0.66 250 mV mV mA k ns ns ns ISC IZ tr, tf tPLH, tPHL VO = GND -0.25V VOUT +0.25V, power-off or no-cable mode RL = 450, CL = 100pF, Figure 8 RL = 450, CL = 100pF, Figure 8 0.9 x |VO| -55 0.05 2 1 +55 +5 mA A s s 4 -6 3.6 -3.6 V 6 -4 V VTH VTH IIN RIN tr, tf tPHL, tPLH |tPHL- tPLH| tSKEWR -7V VCM +7V -7V VCM +7V -10V VA,B +10V -10V VA,B +10V Figures 2, 7 Figures 2, 7 Figures 2, 7 (Note 3) Figures 2, 7 (Notes 3, 4) -0.66 15 30 3 27 3 3 -200 15 +0.66 -50 mV mV mA k ns ns ns ns SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX13171E/MAX13173E/MAX13175E
V.28 TRANSMITTER (All CHANNELS) Output-Voltage Swing Short-Circuit Current Output Leakage Current |VOD| IOH IZ V mA A
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Multiprotocol, Pin-Selectable Data Interface Chipset MAX13171E/MAX13173E/MAX13175E
MAX13173E ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.135V to +5.5V, VL = +1.62V to +5.5V, C1 = C2 = 1F, C3 = C4 = C5 = 4.7F, Figure 15, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, VL = +1.8V, TA = +25C.) (Note 2)
PARAMETER Output Slew Rate Transmitter Input to Output Delay V.28 RECEIVER (All CHANNELS) Input Threshold Low Input Threshold High Input Hysteresis Input Resistance Rise or Fall Time Receiver Input to Output Delay ESD PROTECTION Human Body Model T_OUT, T_OUT/R_IN_, R_IN Air Gap Discharge IEC 61000-4-2 Contact Discharge 15 15 5 kV VIL VIH VHYST RIN tr, tf tPHL, tPLH -15V VIN +15V Figures 5, 11 Figures 5, 11 3 0.8 1.2 1.2 0.25 5 3 150 7 2 V V V k ns ns SYMBOL SRR/F tPHL, tPLH CONDITIONS RL = 3k, CL = 2500pF (swing in 3V) Figures 4, 10 RL = 3k, CL = 2500pF, Figures 4, 10 MIN 4 1 TYP MAX 30 2 UNITS V/s s
MAX13175E ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.135V to +5.5V, VL = +1.62V to +5.5V, C1 = C2 = 1F, C3 = C4 = C5 = 4.7F, Figure 15, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, VL = +1.8V, TA = +25C.) (Note 2)
PARAMETER VCC Operating Range VL Operating Range VDD Operating Range VEE Operating Range VL POR Rising Threshold VCC POR Rising Threshold VDD Supply Current IDD ICC All inputs connected to GND or VL, except no-cable mode All inputs connected to GND or VL, except no-cable mode All inputs connected to GND or VL All inputs connected to GND or VL -1 -3.5 -1 SYMBOL VCC VL VDD VEE CONDITIONS MIN 3.135 1.62 4.5 -7.1 0.7 1 1.06 1.88 0.05 2.15 1.29 TYP MAX 5.5 VCC 7.1 -4 1.46 2.75 0.25 5.9 2.6 +1 UNITS V V V V V V mA mA mA A mA
VCC Supply Current VL Supply Current VEE Supply Current TERMINATOR INPUTS Differential-Mode Impedance V.35 Mode Common-Mode Impedance V.35 Mode
ICC_NOCAB VEE = 0V, M[x] = 1111 (Note 5) IL IEE
-2V VCM +2V, all channels, Figure 12 -2V VCM +2V, all channels, Figure 13
90 135
104 153
110 165

8
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Multiprotocol, Pin-Selectable Data Interface Chipset
MAX13175E ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.135V to +5.5V, VL = +1.62V to +5.5V, C1 = C2 = 1F, C3 = C4 = C5 = 4.7F, Figure 15, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, VL = +1.8V, TA = +25C.) (Note 2)
PARAMETER Differential-Mode Impedance V.11 Mode Differential Path Enable Time Differential Path Disable Time Common-Mode Path Enable Time Common-Mode Path Disable Time High-Impedance Leakage Current Input High Voltage Input Low Voltage Logic Input Current ESD PROTECTION Human Body Model R_A, R_B to GND All Other Pins Air Gap Discharge IEC 61000-4-2 Contact Discharge IEC 61000-4-2 Human Body Model 15 10 6 2 kV kV IZ -15V VR_A +15V -50 SYMBOL CONDITIONS -7V VCM +7V, all channels, except nocable mode, Figure 12 -7V VCM +7V, no cable, VEE = 0V, VAB < 2V, Figure 12 MIN 100 TYP 104 115 50 300 12 2 +50 s s s s A MAX 110 UNITS
MAX13171E/MAX13173E/MAX13175E
LOGIC INPUTS (M0, M1, M2, LATCH, DCE/DTE) VIH VIL IIN VIN = GND or VL -1 0.66 x VL 0.33 x VL +1 V V A
Note 2: All devices are 100% production tested at TA = +85C for the MAX13171E/MAX13173E and TA = +25C for the MAX13175E. Specifications over temperature are guaranteed by design. Note 3: Guaranteed by design, not production tested. Note 4: Output-to-output skews are evaluated as difference of propagation delays between different channels in the same condition and for the same polarity (LH or HL). Note 5: M[x] is the input bus DTE/DCE, M2, M1, M0.
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Multiprotocol, Pin-Selectable Data Interface Chipset MAX13171E/MAX13173E/MAX13175E
MAX13171E Typical Operating Characteristics
(VCC = +3.3V, VL = +1.8V, TA = +25C, unless otherwise noted.)
RS-530 SUPPLY CURRENT vs. DATA RATE
MAX13171E toc01
V.28 SUPPLY CURRENT vs. DATA RATE
MAX13171E toc02
V.35 SUPPLY CURRENT vs. DATA RATE
DCE MODE, FULLY LOADED, ALL TRANSMITTERS OPERATING AT THE SPECIFIED DATA RATE
MAX13171E toc03
350 300 SUPPLY CURRENT (mA) 250 200 150 100 50 0 0.1 10 1000 DCE MODE, R = 50, ALL TRANSMITTERS OPERATING AT THE SPECIFIED DATA RATE
80 70 SUPPLY CURRENT (mA) 60 50 40 30 20 10 0 0 50 100 150 200 DCE MODE, ALL TRANSMITTERS OPERATING AT THE SPECIFIED DATA RATE, RL = 3k, CL = 2500pF
350 300 SUPPLY CURRENT (mA) 250 200 150 100 50 0
10,000
250
0.1
10
1000
10,000
DATA RATE (kbps)
DATA RATE (kbps)
DATA RATE (kbps)
V.11 DIFFERENTIAL OUTPUT VOLTAGE vs. TEMPERATURE
MAX13171E toc04
V.28 OUTPUT VOLTAGE vs. TEMPERATURE
6 OUTPUT VOLTAGE (V) 4 2 0 -2 -4 DC OUTPUT DCE MODE, RL = 3k
MAX13171E toc05
V.35 OUTPUT VOLTAGE vs. TEMPERATURE
MAX13171E toc06
3 DIFFERENTIAL OUTPUT VOLTAGE (V) 2 1 0 -1 -2 -3 -40 -15 10 35 60 DC OUTPUT DCE MODE, R = 50 VOUT+
8 VOUT+
600 400 OUTPUT VOLTAGE (V) 200 0 -200 -400 -600 VOL DC OUTPUT DCE MODE, VCM = 0V, FULL LOAD VOH
VOUT-
VOUT-6 -8 85 -40 -15 10 35 60 85
-40
-15
10
35
60
85
TEMPERATURE (C)
TEMPERATURE (C)
TEMPERATURE (C)
V.35 LOADED DIFFERENTIAL OUTPUT VOLTAGE vs. COMMON-MODE VOLTAGE
MAX13171E toc07
V.11/V.35 RECEIVER INPUT CURRENT vs. INPUT VOLTAGE
MAX13171E toc08
V.28 RECEIVER INPUT CURRENT vs. INPUT VOLTAGE
2.0 1.5 INPUT CURRENT (mA) 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 DC OUTPUT DTE MODE
MAX13171E toc09
560 DC OUTPUT DIFFERENTIAL OUTPUT VOLTAGE (mV) 555 550 |VOD| 545 540 535 530 -4 -2 0 2 4 COMMON-MODE VOLTAGE (V)
500 400 300 INPUT CURRENT (A) 200 100 0 -100 -200 -300 -400 -500 -10 -8 -6 -4 -2 0 2 4 6 8 R2INA, R3INA DC OUTPUT DTE MODE R1INA
2.5
10
-10 -8 -6 -4
-2
0
2
4
6
8
10
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
10
______________________________________________________________________________________
Multiprotocol, Pin-Selectable Data Interface Chipset
MAX13171E Typical Operating Characteristics (continued)
(VCC = +3.3V, VL = +1.8V, TA = +25C, unless otherwise noted.)
MAX13171E/MAX13173E/MAX13175E
V.11 LOOPBACK OPERATION (40Mbps)
MAX13171E toc10
V.28 LOOPBACK OPERATION (250kbps)
MAX13171E toc11
R = 50 T_IN 2V/div T_IN 2V/div
RL = 3k, CL = 2500pF
T_OUT_/R_IN_ 2V/div
T_OUT_/R_IN_ 5V/div
R_OUT 2V/div
R_OUT 2V/div
10ns/div
1s/div
V.35 LOOPBACK OPERATION (40Mbps)
MAX13171E toc12
V.28 SLEW RATE vs. LOAD CAPACITANCE
RL = 3k 30 SLEW RATE (V/s) 25 20 15 10 SRF SRR
MAX13171E toc13
35
FULL LOAD T_IN 2V/div
T_OUT_/R_IN_ 0.5V/div
R_OUT 2V/div
5 0 1s/div 0 1000 2000 3000 4000 5000 LOAD CAPACITANCE (pF)
V.11/V.35 RECEIVER PROPAGATION DELAY vs. TEMPERATURE
18 PROPAGATION DELAY (ns) 16 14 12 10 8 6 4 2 0 -40 -15 10 35 60 85 TEMPERATURE (C) 0 -40 tPHL tPLH
MAX13171E toc14
V.11 TRANSMITTER PROPAGATION DELAY vs. TEMPERATURE
tPLH PROPAGATION DELAY (ns) 20 tPHL
MAX13171E toc15
V.35 TRANSMITTER PROPAGATION DELAY vs. TEMPERATURE
MAX13171E toc16
20
25
30 25 PROPAGATION DELAY (ns) 20 15 10 5 0 tPHL tPLH
15
10
5
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (C)
TEMPERATURE (C)
______________________________________________________________________________________
11
Multiprotocol, Pin-Selectable Data Interface Chipset MAX13171E/MAX13173E/MAX13175E
MAX13173E Typical Operating Characteristics
(VCC = +3.3V, VL = +1.8V, TA = +25C, unless otherwise noted.)
R-530 SUPPLY CURRENT vs. DATA RATE
MAX13171E toc17
V.28 SUPPLY CURRENT vs. DATA RATE
MAX13171E toc18
V.11 DIFFERENTIAL OUTPUT VOLTAGE vs. TEMPERATURE
DIFFERENTIAL OUTPUT VOLTAGE (V) 3 2 1 0 -1 -2 -3 -4 -40 -15 10 35 60 85 DC OUTPUT DCE MODE, INVERT = 1, R = 50 VOUTVOUT+
MAX13171E toc19
250 DCE MODE, INVERT = 1 3 TRANSMITTERS OPERATING AT THE SPECIFIED DATA RATE IN V.11 MODE
90 80 SUPPLY CURRENT (mA) 70 60 50 NO LOAD 40 30 20 DCE MODE, INVERT = 1 ALL TRANSMITTERS OPERATING AT THE SPECIFIED DATA RATE 0 50 100 150 200 FULL LOAD, RL = 50, CL = 2500pF
4
200 SUPPLY CURRENT (mA)
150
100
FULL LOAD, R = 50
50 NO LOAD, R = 1.95k 0 0 10 1000 100,000 DATA RATE (kbps)
10 0
250
DATA RATE (kbps)
TEMPERATURE (C)
V.10 OUTPUT VOLTAGE vs. TEMPERATURE
MAX13171E toc20
V.28 OUTPUT VOLTAGE vs. TEMPERATURE
6 OUTPUT VOLTAGE (V) 4 2 0 -2 -4 DC OUTPUT DCE MODE, RL = 3k
MAX13171E toc21
8 6 OUTPUT VOLTAGE (V) 4 2 0 -2 VOUT-4 -6 -8 -40 -15 10 35 60 RL = 3.9k DC OUTPUT DCE MODE RL = 450 RL = 3.9k VOUT+
8 VOUT+
-6 -8 85 -40 -15 10
VOUT-
35
60
85
TEMPERATURE (C)
TEMPERATURE (C)
V.11 RECEIVER INPUT CURRENT vs. INPUT VOLTAGE
MAX13171E toc22
V.28 RECEIVER INPUT CURRENT vs. INPUT VOLTAGE
DC OUTPUT 3 INPUT CURRENT (mA) 2 1 0 -1 -2 -3 -4
MAX13171E toc23
500 400 300 INPUT CURRENT (V) 200 100 0 -100 -200 -300 -400 -500 -10 -8 -6 -4 -2 0 2 4 6 8 R1INA R3INA R2INA DC OUTPUT DCE MODE
4
10
-15
-10
-5
0
5
10
15
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
12
______________________________________________________________________________________
Multiprotocol, Pin-Selectable Data Interface Chipset
MAX13173E Typical Operating Characteristics (continued)
(VCC = +3.3V, VL = +1.8V, TA = +25C, unless otherwise noted.)
MAX13171E/MAX13173E/MAX13175E
V.28 SLEW RATE vs. LOAD CAPACITANCE
MAX13171E toc24
V.10 TRANSMITTER RISE/FALL TIME vs. LOAD CAPACITANCE
MAX13171E toc25
V.11 LOOPBACK OPERATION (40Mbps)
MAX13171E toc26
35 RL = 3k 30 SLEW RATE (V/s) 25 20 15 10 5 0 0 1000 2000 3000 4000 SRR SRF
2.0 1.8 1.6 RISE/FALL TIME (s) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 RISE FALL
FULL LOAD T_IN 2V/div
T_OUT_/R_IN_ 2V/div
R_OUT 2V/div
5000
0
1000
2000
3000
4000
5000
10ns/div
LOAD CAPACITANCE (pF)
LOAD CAPACITANCE (pF)
V.28 LOOPBACK OPERATION (250kbps)
MAX13171E toc27
V.10 LOOPBACK OPERATION (100kbps)
MAX13171E toc28
RL = 3k, CL = 2500pF T_IN 2V/div T_IN 2V/div RL = 3.9k T_OUT_/R_IN_ 5V/div T_OUT_/R_IN_ 5V/div RL = 450 R_OUT 2V/div R_OUT 2V/div
1s/div
4s/div
V.11 RECEIVER PROPAGATION DELAY vs. TEMPERATURE
MAX13171E toc29
V.11 TRANSMITTER PROPAGATION DELAY vs. TEMPERATURE
MAX13171E toc30
25 tPHL tPLH 15
25
PROPAGATION DELAY (ns)
PROPAGATION DELAY (ns)
20
20
tPHL tPLH
15
10
10
5
5
0 -40 -15 10 35 60 85 TEMPERATURE (C)
0 -40 -15 10 35 60 85 TEMPERATURE (C)
______________________________________________________________________________________
13
Multiprotocol, Pin-Selectable Data Interface Chipset MAX13171E/MAX13173E/MAX13175E
MAX13175E Typical Operating Characteristics
(VCC = +3.3V, VL = +1.8V, TA = +25C, unless otherwise noted.)
V.11 OR V.35 DIFFERENTIAL IMPEDANCE vs. TEMPERATURE
MAX13175E toc31
MAX13175E toc32
109 108 IMPEDANCE (I) 107 106 105 104 103 102 101 100 -40 -15 10 35 60 VCM = -7V VCM = +7V VCM = 0V
109 108 IMPEDANCE (I) 107 106 105 104 103 102 101 100
109 108 IMPEDANCE (I) 107 106 105 104 103 102 101 100
85
-7
-5
-3
-1
1
3
5
7
3.0
3.5
4.0
4.5
5.0
5.5
TEMPERATURE (NC)
VCM (V)
VCC (V)
V.11 OR V.35 DIFFERENTIAL IMPEDANCE vs. SUPPLY VOLTAGE (VEE)
MAX13175E toc34
MAX13175E toc35
109 108 IMPEDANCE (I) 107 106 105 104 103 102 101 100 -7 -6 VEE (V) -5
160 IMPEDANCE (I) 155 150 145 140 135 VCM = -2V VCM = +2V
180 175 IMPEDANCE (I) 170 165 160 155 150 145 140 135
-4
-40
-15
10
35
60
85
-2
-1
0 VCM (V)
1
2
TEMPERATURE (NC)
14
______________________________________________________________________________________
MAX13175E toc36
110
V.35 COMMON-MODE IMPEDANCE vs. TEMPERATURE
165 185
V.35 COMMON-MODE IMPEDANCE vs. COMMON-MODE VOLTAGE (VCM)
MAX13175E toc33
110
110
V.11 OR V.35 DIFFERENTIAL IMPEDANCE vs. COMMON-MODE VOLTAGE (VCM)
110
V.11 OR V.35 DIFFERENTIAL IMPEDANCE vs. SUPPLY VOLTAGE (VCC)
Multiprotocol, Pin-Selectable Data Interface Chipset
MAX13175E Typical Operating Characteristics (continued)
(VCC = +3.3V, VL = +1.8V, TA = +25C, unless otherwise noted.)
MAX13171E/MAX13173E/MAX13175E
V.35 COMMON-MODE IMPEDANCE vs. SUPPLY VOLTAGE
MAX13175E toc37
MAX13175E toc38
160 IMPEDANCE (I) 155 150 145 140 135 VCM = -2V VCM = +2V
160 IMPEDANCE (I) 155 150 145 140 135 VCM = -2V VCM = +2V
700 SUPPLY CURRENT (FA) 600 500 400 300 200 100 IEE ICC
3.0
3.5
4.0
4.5
5.0
5.5
-7
-6 VEE (V)
-5
-4
0
-40
-15
10
35
60
85
VCC (V)
TEMPERATURE (NC)
V.11 OR V.35 DIFFERENTIAL IMPEDANCE MAGNITUDE vs. FREQUENCY
M AX13175E t 40 oc
V.11 OR V.35 DIFFERENTIAL IMPEDANCE PHASE vs. FREQUENCY
10 5 PHASE (DEGREES) 0 -5 -10 -15 -20 -25 -30
M AX13175E t 41 oc
120 100 I PEDANCE ( ) M I 80 60 40 20 0 0.1 1 10
15
-35 100 0.1 1 10 100 FREQUENCY (MHz) FREQUENCY (MHz)
______________________________________________________________________________________
15
MAX13175E toc39
165
165
V.35 COMMON-MODE IMPEDANCE vs. SUPPLY VOLTAGE (VEE)
800
HI-Z MODE SUPPLY CURRENT vs. TEMPERATURE
Multiprotocol, Pin-Selectable Data Interface Chipset MAX13171E/MAX13173E/MAX13175E
MAX13171E Pin Description
PIN 1, 2, 6, 30, 31 3, 16 4 5 7 8 9 10 11 12 13 14 15 17 18 19, 24, 29, 35 20 21 22 23 25 26 27 28 32 33 34 36 37 38 NAME N.C. VCC T1IN T2IN T3IN R1OUT R2OUT R3OUT M0 VL M1 M2 DCE/DTE R3INB R3INA GND R2INB R2INA T3OUTB/R1INB T3OUTA/R1INA T2OUTB T2OUTA T1OUTB T1OUTA VEE C2C2+ C1C1+ VDD No Connection. Not internally connected. Device Supply Voltage. Bypass VCC with a 4.7F capacitor to ground as close as possible to pin 3. Transmitter 1 Logic Input Transmitter 2 Logic Input Transmitter 3 Logic Input Receiver 1 Logic Output with Internal Pullup to VL Receiver 2 Logic Output with Internal Pullup to VL Receiver 3 Logic Output with Internal Pullup to VL Mode-Select 0 Input with Internal Pullup to VL Logic-Supply Reference Input. VL determines the voltage level of the logic interface. Bypass VL with a 0.1F capacitor to ground as close as possible to the device. Mode-Select 1 Input with Internal Pullup to VL Mode-Select 2 Input with Internal Pullup to VL DCE/DTE Mode-Select Input with Internal Pullup to VL Receiver 3 Noninverting Input Receiver 3 Inverting Input Ground Receiver 2 Noninverting Input Receiver 2 Inverting Input Transmitter 3 Noninverting Output/Receiver 1 Noninverting Input Transmitter 3 Inverting Output/Receiver 1 Inverting Input Transmitter 2 Noninverting Output Transmitter 2 Inverting Output Transmitter 1 Noninverting Output Transmitter 1 Inverting Output Charge-Pump Negative Supply Output. Connect a 4.7F ceramic capacitor from VEE to ground as close as possible to the device. VEE Charge-Pump Flying-Capacitor Negative Terminal. Connect a 1F ceramic capacitor between C2+ and C2-. VEE Charge-Pump Flying-Capacitor Positive Terminal. Connect a 1F ceramic capacitor between C2+ and C2-. VDD Charge-Pump Flying-Capacitor Negative Terminal. Connect a 1F ceramic capacitor between C1+ and C1-. VDD Charge-Pump Flying-Capacitor Positive Terminal. Connect a 1F ceramic capacitor between C1+ and C1-. Charge-Pump Positive-Supply Output. Connect a 4.7F ceramic capacitor from VDD to ground as close as possible to the device. Exposed Pad. Internally connected to VEE. Connect to a large VEE plane to maximize thermal performance. Not intended as an electrical connection point. Do not share the same plane as the MAX13173E. FUNCTION
--
EP
16
______________________________________________________________________________________
Multiprotocol, Pin-Selectable Data Interface Chipset MAX13171E/MAX13173E/MAX13175E
MAX13173E Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18, 25, 31, 35 19 20 21 22 23 24 26 27 28 29 30 32 33 34 36 NAME T1IN VCC T2IN T3IN VL R1OUT R2OUT R3OUT R5OUT/T5IN T4IN R4OUT M0 M1 M2 DCE/DTE INVERT Transmitter 1 Logic Input Device Supply Voltage. Bypass VCC with a 4.7F capacitor to ground as close as possible to the device. Transmitter 2 Logic Input Transmitter 3 Logic Input Logic-Supply Reference Input. VL determines the voltage level of the logic interface. Bypass VL with a 0.1F capacitor to ground, as close as possible to the device. Receiver 1 Logic Output with Internal Pullup to VL Receiver 2 Logic Output with Internal Pullup to VL Receiver 3 Logic Output with Internal Pullup to VL Receiver 5 Logic Output/Transmitter 5 Logic Input Transmitter 4 Logic Input Receiver 4 Logic Output Mode-Select 0 Input with Internal Pullup to VL Mode-Select 1 Input with Internal Pullup to VL Mode-Select 2 Input with Internal Pullup to VL DCE/DTE Mode-Select Input with Internal Pullup to VL T4/R4 and T5/R5 Select Input with Internal Pullup to VL. INVERT reverses the action of DCE/DTE for channels 4 and 5. Ground Receiver 3 Noninverting Input Receiver 3 Inverting Input Receiver 2 Noninverting Input Receiver 2 Inverting Input FUNCTION
T4OUTA/R4INA Transmitter 4 Inverting Output/Receiver 4 Inverting Input GND R3INB R3INA R2INB R2INA
T3OUTB/R1INB Transmitter 3 Noninverting Output/Receiver 1 Noninverting Input T3OUTA/R1INA Transmitter 3 Inverting Output/Receiver 1 Inverting Input T2OUTB T2OUTA T1OUTB T1OUTA Transmitter 2 Noninverting Output Transmitter 2 Inverting Output Transmitter 1 Noninverting Output Transmitter 1 Inverting Output Charge-Pump Negative-Supply Output. Connect a 4.7F ceramic capacitor from VEE to ground as close as possible to the device. VEE Charge-Pump Flying-Capacitor Negative Terminal. Connect a 1F ceramic capacitor between C2+ and C2-. VEE Charge-Pump Flying-Capacitor Positive Terminal. Connect a 1F ceramic capacitor between C2+ and C2-. VDD Charge-Pump Flying-Capacitor Negative Terminal. Connect a 1F ceramic capacitor between C1+ and C1-.
T5OUTA/R5INA Transmitter 5 Inverting Output/Receiver 5 Inverting Input VEE C2C2+ C1-
______________________________________________________________________________________
17
Multiprotocol, Pin-Selectable Data Interface Chipset MAX13171E/MAX13173E/MAX13175E
MAX13173E Pin Description (continued)
PIN 37 38 NAME C1+ VDD FUNCTION VDD Charge-Pump Flying-Capacitor Positive Terminal. Connect a 1F ceramic capacitor between C1+ and C1-. Charge-Pump Positive-Supply Output. Connect a 4.7F ceramic capacitor from VDD to ground as close as possible to the device. Exposed Pad. Internally connected to VEE. Connect to a large VEE plane to maximize thermal performance, not intended as an electrical connection point. Does not share the same plane as the MAX13171E.
--
EP
MAX13175E Pin Description
PIN 1, 38 2, 3 4, 5 6, 7 8 9, 10 11, 12 13, 18 14 15 16 17 19 20, 21 22, 23 24, 25 26, 27 28, 29 30, 31 32 33 34 35 36 37 -- NAME R1B R1A R2A R2B R2C R3A R3B GND R3C VL VEE VDD VCC R4B R4A R5B R5A R6A R6B DCE/DTE LATCH M2 M1 M0 R1C EP Load 1, Node B Load 1, Node A Load 2, Node A Lode 2, Node B Lode 2, Center Tap Load 3, Node A Lode 3, Node B Ground Lode 3, Center Tap Logic-Supply Reference Input. VL determines the voltage level of the logic interface. Negative Supply Voltage. Bypass VEE to GND with a 0.1F capacitor. Connect to VEE from the MAX13173E. Positive Supply Voltage. Bypass VDD to GND with a 0.1F capacitor. Connect to VDD from the MAX13173E. Supply Voltage. Bypass VCC to GND with a 0.1F capacitor as close as possible to the device. Load 4, Node B Load 4, Node A Load 5, Node B Load 5, Node A Load 6, Node A Load 6, Node B DCE/DTE Mode-Select Input Latch Signal Input. When LATCH is low, the input latches are transparent. When LATCH is high, the data at the mode-select inputs are latched. Mode-Select Input 2 Mode-Select Input 1 Mode-Select Input 0 Load 1, Center Tap Exposed Pad. Internally connected to VEE. Connect to a large VEE plane to maximize thermal performance, not intended as an electrical connection point. If VEE is powered from the MAX13173E's VEE, planes can be shared. FUNCTION
18
______________________________________________________________________________________
Multiprotocol, Pin-Selectable Data Interface Chipset
Test Circuits
A
100pF
MAX13171E/MAX13173E/MAX13175E
R VOD
T
B 100 A
B A
R
15pF
R B
VOC
100pF
Figure 1. V.11 DC Test Circuit
Figure 2. V.11 AC Test Circuit
50 T B VOD A 50 125 VCM 125
50 B R
50
A 15pF
Figure 3. V.35 Transmitter/Receiver Test Circuit
T
A
T
A
R
VO CL
RL
15pF
Figure 4. V.10/V.28 Transmitter Test Circuit
Figure 5. V.10/V.28 Receiver Test Circuit
______________________________________________________________________________________
19
Multiprotocol, Pin-Selectable Data Interface Chipset MAX13171E/MAX13173E/MAX13175E
Timing Diagrams
VL TIN_ 0V V0 B-A -V0 50% tR VL/2 tPLH 90% 10%
f = 1MHz: tr, tf 1ns
VL/2 tPHL 90% tF 50% 10%
Figure 6. V.11 Transmitter Propagation Delays
+1V B-A -1V tPLH V0H R V0L VL/2 tR 90% 10% OUTPUT tPHL 90% 10% tF VL/2 0 f = 1MHz: tr, tf 1ns INPUT 0
Figure 7. V.11 Receiver Propagation Delays
VL TIN_ 0V V0H A -V0L tF VL/2 tPHL 90% 0 10% 10% tR 0 tR, tF 10ns VL/2 tPLH 90%
Figure 8. V.10 Transmitter Propagation Delay
VIH A VIL V0H R V0L 0 tPHL VL/2 tF 90% 10% tR, tF 10ns 0 tPLH 90% 10% tR VL/2
Figure 9. V.10 Receiver Propagation Delay
20 ______________________________________________________________________________________
Multiprotocol, Pin-Selectable Data Interface Chipset
Timing Diagrams (continued)
VL TIN_ 0V V0H A -V0L tF VL/2 tPHL 3V 0 -3V SRF = 6/tF SRR = 6/tR -3V tR 0 tR, tF 10ns VL/2 tPLH 3V
MAX13171E/MAX13173E/MAX13175E
Figure 10. V.28 Transmitter Propagation Delay
(2.0V) VIH A (0.8V) VIL V0H R V0L 1.3V tPHL VL/2 tF 90% 10% tR, tF 10ns 1.3V tPLH 90% 10% tR VL/2
Figure 11. V.28 Receiver Propagation Delay
A A
I
R1 = 52 R1 = 52
AMMETER
S1 ON R3 = 127 S2 OFF S1 ON R3 = 127 AMMETER S2 ON R2 = 52 I R2 = 52 VCM = 2V B VCM = 7V OR 2V V RDM = DM I V RCM = CM I B
VDM = 2V
Figure 12. V.11 or V.35 Differential Impedance Measurement
Figure 13. V.35 Common-Mode Impedance Measurement
21
______________________________________________________________________________________
Multiprotocol, Pin-Selectable Data Interface Chipset MAX13171E/MAX13173E/MAX13175E
VCC R1C VDD R2C R3C VL
VEE
EP
MAX13175E
LATCH
VEE
GND R1A R1B R2A R2B R3A R3B R4A R4B R5A R5B R6A R6B
DCE/DTE M2 M1 M0
Figure 14. MAX13175E Block Diagram
Detailed Description
The MAX13171E/MAX13173E/MAX13175E form a complete pin-selectable DTE or DCE interface port that supports the V.28 (RS-232), V.10/V.11 (RS-449/V.36, RS-530, RS-530A, X.21), and V.35 protocols. The MAX13171E transceivers carry the high-speed clock and data signals, while the MAX13173E transceivers carry serial-interface control signaling. The MAX13171E can be terminated by the MAX13175E pin-selectable resistor termination network, or by a discrete termination network. The MAX13171E/MAX13173E feature a low supply current, no-cable mode, true fail-safe operation, and thermal-shutdown circuitry. Thermal shutdown protects the drivers against excessive power dissipation. When activated, the thermal-shutdown circuitry places the driver and receiver outputs into a highimpedance state. The MAX13171E is a three-driver/three-receiver, multiprotocol transceiver that operates from a single +3.135V to +5.5V supply. The MAX13173E is a five-driver/five-receiver multiprotocol transceiver that operates from a single +3.135V to +5.5V supply. The MAX13175E contains six pin-selectable multiprotocol cable termination networks (Figure 14). Each network is capable of terminating V.11 (RS-422, RS-530, RS-530A, RS-449, V.36 and X.21) with a 100 differential load, V.35 with a T-network load, or V.28 (RS-232) and V.10 (RS-423) with an open-circuit load for use with transceivers having on-chip termination. The terminations and protocols are pin selectable. The MAX13175E replaces discrete resistor termination networks and
expensive relays required for multiprotocol termination, saving space and cost.
Dual Charge-Pump Voltage Converter
The MAX13171E/MAX13173E have internal-regulated dual charge pumps that provide positive and negative output voltages from a single supply. The charge pump operates in discontinuous mode. If the output voltage is less than the regulated voltage, the charge pump is enabled. If the output voltage exceeds the regulated voltage, the charge pump is disabled. Each charge pump requires flying capacitors (C1, C2), and reservoir capacitors (C3, C5), to generate the VDD and VEE supplies. Figure 15 shows the charge-pump connections.
MAX13171E MAX13173E
VDD C3 4.7F C1+ C1 1F C1+3.135V TO +5.5V C4 4.7F VEE C5 4.7F VCC GND C2+ C2 1F C2-
Figure 15. Charge Pump
22
______________________________________________________________________________________
Multiprotocol, Pin-Selectable Data Interface Chipset
Fail-Safe
The MAX13171E/MAX13173E guarantee a logic-high receiver output when the receiver inputs are shorted, or when they are connected to a terminated transmission line with all drivers disabled by setting the receiver threshold between -50mV and -200mV in the V.11 and V.35 modes. If the differential receiver input voltage (B A) is -50mV, R_OUT is logic-high. If (B - A) is -200mV, R_OUT is logic-low. In the case of a terminated bus with all transmitters disabled, the receiver's differential input voltage is pulled to zero by the termination. This results in a logic-high with a 50mV minimum noise margin. The V.10 receiver threshold is set between 50mV and 250mV. If the V.10 receiver input voltage is less than or equal to 50mV, R_OUT is logic-high. The V.28 receiver threshold is set between 0.8V and 2.0V. If the receiver input voltage is less than or equal to 0.8V, R_OUT is logic-high. In the case of a terminated bus with transmitters disabled, the receiver's input voltage is pulled to GND by the termination.
Mode Selection
The mode-select inputs M0, M1, and M2 determine which interface protocol is selected (Table 1 for the MAX13171E, Table 2 for the MAX13173E). The state of the DCE/DTE input determines whether the transceivers are configured as a DTE serial port or a DCE serial port. The INVERT input on the MAX13173E changes the DCE/DTE functionality regarding T4/T5 and R4/R5 only. M0, M1, M2, INVERT, and DCE/DTE are internally pulled up to VL to ensure logic-high if left unconnected. If the M0, M1, and M2 mode inputs are all unconnected, the MAX13171E/MAX13173E enter no-cable mode. The MAX13175E mode select inputs and DCE/DTE input do not have an internal pullup to VL. They are pulled logic-high if their mode-select inputs are tied to the MAX13171E/MAX13173E's mode select inputs.
MAX13171E/MAX13173E/MAX13175E
Termination Modes
The termination networks in the MAX13175E can be set to one of three modes, V.11, V.35, or high impedance.
Table 1. MAX13171E Mode Selection
MAX13171E MODE NAME Not Used (Default V.11) RS-530A RS-530 X.21 V.35 RS-449/V.36 V.28/RS-232 No Cable Not Used (Default V.11) RS-530A RS-530 X.21 V.35 RS-449/V.36 V.28/RS-232 No Cable M2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 M1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 M0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DCE/ DTE 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 T1 V.11 V.11 V.11 V.11 V.35 V.11 V.28 Z V.11 V.11 V.11 V.11 V.35 V.11 V.28 Z T2 V.11 V.11 V.11 V.11 V.35 V.11 V.28 Z V.11 V.11 V.11 V.11 V.35 V.11 V.28 Z T3 Z Z Z Z Z Z Z Z V.11 V.11 V.11 V.11 V.35 V.11 V.28 Z R1 V.11 V.11 V.11 V.11 V.35 V.11 V.28 Z Z Z Z Z Z Z Z Z R2 V.11 V.11 V.11 V.11 V.35 V.11 V.28 Z V.11 V.11 V.11 V.11 V.35 V.11 V.28 Z R3 V.11 V.11 V.11 V.11 V.35 V.11 V.28 Z V.11 V.11 V.11 V.11 V.35 V.11 V.28 Z
______________________________________________________________________________________
23
Multiprotocol, Pin-Selectable Data Interface Chipset MAX13171E/MAX13173E/MAX13175E
Table 2. MAX13173E Mode Selection
PROTOCOL Not Used (Default V.11) RS-530A RS-530 X.21 V.35 RS-449/V.36 V.28/RS-232 No Cable Not Used (Default V.11) RS-530A RS-530 X.21 V.35 RS-449/V.36 V.28/RS-232 No Cable Not Used (Default V.11) RS-530A RS-530 X.21 V.35 RS-449/V.36 V.28/RS-232 No Cable Not Used (Default V.11) RS-530A RS-530 X.21 V.35 RS-449/V.36 V.28/RS-232 No Cable M2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 M1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 M0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DCE/ DTE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 INVERT 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 T1 V.11 V.11 V.11 V.11 V.28 V.11 V.28 Z V.11 V.11 V.11 V.11 V.28 V.11 V.28 Z V.11 V.11 V.11 V.11 V.28 V.11 V.28 Z V.11 V.11 V.11 V.11 V.28 V.11 V.28 Z T2 V.11 V.10 V.11 V.11 V.28 V.11 V.28 Z V.11 V.10 V.11 V.11 V.28 V.11 V.28 Z V.11 V.10 V.11 V.11 V.28 V.11 V.28 Z V.11 V.10 V.11 V.11 V.28 V.11 V.28 Z T3 Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z V.11 V.11 V.11 V.11 V.28 V.11 V.28 Z V.11 V.11 V.11 V.11 V.28 V.11 V.28 Z R1 V.11 V.11 V.11 V.11 V.28 V.11 V.28 Z V.11 V.11 V.11 V.11 V.28 V.11 V.28 Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z R2 V.11 V.10 V.11 V.11 V.28 V.11 V.28 Z V.11 V.10 V.11 V.11 V.28 V.11 V.28 Z V.11 V.10 V.11 V.11 V.28 V.11 V.28 Z V.11 V.10 V.11 V.11 V.28 V.11 V.28 Z R3 V.11 V.11 V.11 V.11 V.28 V.11 V.28 Z V.11 V.11 V.11 V.11 V.28 V.11 V.28 Z V.11 V.11 V.11 V.11 V.28 V.11 V.28 Z V.11 V.11 V.11 V.11 V.28 V.11 V.28 Z T4 Z Z Z Z Z Z Z Z V.10 V.10 V.10 V.10 V.28 V.10 V.28 Z V.10 V.10 V.10 V.10 V.28 V.10 V.28 Z Z Z Z Z Z Z Z Z R4 V.10 V.10 V.10 V.10 V.28 V.10 V.28 Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z V.10 V.10 V.10 V.10 V.28 V.10 V.28 Z T5 Z Z Z Z Z Z Z Z V.10 V.10 V.10 V.10 V.28 V.10 V.28 Z V.10 V.10 V.10 V.10 V.28 V.10 V.28 Z Z Z Z Z Z Z Z Z R5 V.10 V.10 V.10 V.10 V.28 V.10 V.28 Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z V.10 V.10 V.10 V.10 V.10 V.28 V.10 V.28 Z
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Multiprotocol, Pin-Selectable Data Interface Chipset
As shown in Figure 16, in V.11 mode, switch S1 is closed and switch S2 is open, presenting 104 across terminals A and B. In V.35 mode, switches S1 and S2 are both closed, presenting a T-network with 104 differential impedance and 153 common-mode impedance. In high-impedance mode, switches S1 and S2 are both open, presenting a high impedance across terminals A and B suitable for V.28 and V.10 modes. The state of the MAX13175E's mode-select inputs, M0, M1, M2, and DCE/DTE determines the mode of each of the six termination networks. Table 3 shows a cross-reference of termination mode and select input state for each of the six termination networks within the MAX13175E.
MAX13171E/MAX13173E/MAX13175E
A MAX13175E R1 52
A MAX13175E R1 52
A MAX13175E R1 52
S1 CLOSED C S2 OPEN R2 52 R3 127
S1 CLOSED C S2 CLOSED R2 52 R3 127
S1 OPEN C S2 OPEN R2 52 R3 127
B
B
B
(a) V.11
Figure 16. Termination Modes
(b) V.35
(c) Z
Table 3. MAX13175E Termination Mode Selection
PROTOCOL V.10/RS-423 RS-530A RS-530 X.21 V.35 RS-449/V.36 V.28/RS-232 No Cable V.10/RS-423 RS-530A RS-530 X.21 V.35 RS-449/V.36 V.28/RS-232 No Cable DCE/DTE 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 M2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 M1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 M0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 R1 Z Z Z Z V.35 Z Z V.11 Z Z Z Z V.35 Z Z V.11 R2 Z Z Z Z V.35 Z Z V.11 Z Z Z Z V.35 Z Z V.11 R3 Z Z Z Z Z Z Z V.11 Z Z Z Z V.35 Z Z V.11 R4 Z V.11 V.11 V.11 V.35 V.11 Z V.11 Z Z Z Z Z Z Z V.11 R5 Z V.11 V.11 V.11 V.35 V.11 Z V.11 Z V.11 V.11 V.11 V.35 V.11 Z V.11 R6 Z V.11 V.11 V.11 V.35 V.11 Z V.11 Z V.11 V.11 V.11 V.35 V.11 Z V.11
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Multiprotocol, Pin-Selectable Data Interface Chipset MAX13171E/MAX13173E/MAX13175E
No-Cable Mode
The MAX13171E/MAX13173E enter no-cable mode when the mode-select inputs are left unconnected or connected high (M0 = M1 = M2 = 1). The receiver outputs enter a high-impedance state in no-cable mode, allowing these output lines to be shared with other receiver outputs (the receiver outputs have an internal pullup resistor to pull the outputs high if not driven). Also, in no-cable mode, the transmitter outputs enter a high-impedance state, so these output lines can be shared with other devices. The MAX13175E enters no-cable mode when the mode select inputs, M0, M1, and M2 are connected high. In no-cable mode, all six termination networks are placed in V.11 mode, with S1 closed and S2 open. minimum value of 4.7F (Figure 15). To reduce the ripple present on the transmitter outputs, capacitors C3, C4, and C5 can be increased. The values of C1 and C2 should not be increased.
Cable Mode-Select Application
A cable-selectable multiprotocol interface is shown in Figure 17. The mode control lines M0, M1, and DCE/DTE are wired to the DB-25 connector. To select the serial interface mode, the appropriate combination of M0, M1, and DCE/DTE are grounded within the cable wiring. The control lines that are not grounded are pulled high by the internal pullups on the MAX13171E/MAX13173E. The serial interface protocol of the MAX13171E/ MAX13173E/MAX13175E is selected based on the cable that is connected to the DB-25 interface.
VL Logic Supply The MAX13171E/MAX13173E/MAX13175E include a VL logic supply that allows user-defined interface logicvoltage levels referenced to VL. VL can go down to +1.62V and up to VCC. All logic inputs and outputs are referred to VL. Data Rate
The MAX13171E/MAX13173E/MAX13175E support a maximum data rate of 40Mbps in RS-449/V.36, RS-530, RS-530A, X.21, V.35 if only one of the MAX13171E high-speed transceivers is operated at the maximum data rate. If two high-speed transceivers operate simultaneously, the maximum data rate is 20Mbps.
V.10 (RS-423) Interface (MAX13173E Only)
The V.10 interface (Figure 18) is an unbalanced singleended interface capable of driving a 450 load. The V.10 driver generates a minimum VO voltage of 4V across A' and C' when unloaded, and a minimum voltage of 0.9 x V O when loaded with 450. The V.10 receiver has a single-ended input and does not reject common-mode differences between C and C'. The V.10 receiver-input trip threshold is defined between +50mV and +250mV with input impedance characteristic shown in Figure 19. The MAX13173E V.10 mode receiver has a threshold between +50mV and +250mV. To ensure that the receiver has proper fail-safe operation, see the FailSafe section. To aid in rejecting system noise, the MAX13173E V.10 receiver has a typical hysteresis of 25mV. Switch S3 in Figures 20a and 20b is open in V.10 mode to disable the V.28 5k termination at the receiver input. Switch S4 is closed and switch S5 is open to internally ground the receiver B input.
Applications Information
Capacitor Selection
The capacitors used for the charge pumps, as well as for supply bypassing, must have a low equivalent series resistance (ESR), low inductance (ESL), and low temperature coefficient. Multilayer ceramic capacitors with an X7R dielectric offer the best combination of performance, size, and cost. The flying capacitors (C1, C2) should have a value of 1F, while the bypass capacitor (C4) and reservoir capacitors (C3, C5) should have a
26
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Multiprotocol, Pin-Selectable Data Interface Chipset MAX13171E/MAX13173E/MAX13175E
VCC C4 4.7F 100pF 100pF 100pF VCC 0.1F VDD VL 0.1F
MAX13175E
DCE/DTE M2 M1 R1A R1B R2A R2B R3A R3B R4A R4B R5A R5B R6A R6B C1 1F VDD C3 4.7F CHARGE PUMP VEE C5 4.7F T1OUTA T1OUTB T2OUTA T2OUTB VEE 0.1F C2 1F 0.1F LATCH M0
VL
DTE_TXD/DCE_RXD DTE_SCTE/DCE_RXC
T1IN T2IN T3IN
T1 T2 T3 R1 R2 R3
DTE 2 TXD A 14 TXD B 24 SCTE A 11 SCTE B 15 12 17 9 3 16 7
DCE RXD A RXD B RXC A RXC B
DTE_TXC/DCE_TXC DTE_RXC/DCE_SCTE DTE_RXD/DCE_TXD VL 0.1F
R1OUT R2OUT R3OUT
T3OUTA/R1INA T3OUTB/R1INB R2INA R2INB R3INA R3INB
TXC A TXC B
TXC A TXC B
RXC A SCTE A RXC B SCTE B RXD A TXD A RXD B TXD B SG
NC
MAX13171E M0 M1 M2
DCE/DTE
1
SHIELD
DB-25 CONNECTOR C4 4.7F VCC C1 1F VDD C3 4.7F CHARGE PUMP VEE C5 4.7F T1OUTA DTE_RTS/DCE_CTS DTE_DTR/DCE_DSR T1IN T2IN T3IN DTE_DCD/DCE_DCD R1OUT DTE_DSR/DCE_DTR R2OUT DTE_CTS/DCE_RTS R3OUT T4IN R4OUT R5OUT/T5IN VL 0.1F T5 R5 T1 T2 T3 R1 R2 R3 T4 R4 T5OUTA/R5INA T3OUTA/R1INA T3OUTB/R1INB R2INA R2INB R3INA R3INB T4OUTA/R4INA 8 DCD A 10 DCD B 6 DSR A 22 DSR B 5 CTS A 13 CTS B DCD A DCD B DTR A DTR B RTS A RTS B T1OUTB T2OUTA T2OUTB C2 1F 25 DCE/DTE 21 M1 18 M0 4 19 20 23 RTS A RTS B DTR A DTR B CTS A CTS B DSR A DSR B
NC
MAX13173E M0 M1 M2 DCE/DTE INVERT
Figure 17. Cable-Selectable Multiprotocol DCE/DTE Port with DB-25 Connector
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Multiprotocol, Pin-Selectable Data Interface Chipset MAX13171E/MAX13173E/MAX13175E
GENERATOR UNBALANCED INTERCONNECTING CABLE CABLE TERMINATION LOAD RECEIVER
A
A
C
C
Figure 18. Typical V.10/V.28 Interface
IZ
+3.25mA
-10V
-3V +3V VZ +10V
-3.25mA
Figure 19. Receiver Input Impedance Curve
A
A R5 55k R8 5k R6 11k
A
A R5 55k R8 5k R6 11k
MAX13171E MAX13173E
MAX13173E
RECEIVER S3
RECEIVER
S3 + 1.4V R7 11k B B R4 55k S2 GND S1
C
C GND
Figure 20a. V.10 Internal Resistance Network for Receivers 1, 2, and 3
28
Figure 20b. V.10 Internal Resistance Network for Receivers 4 and 5
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Multiprotocol, Pin-Selectable Data Interface Chipset
V.11 (RS-422) Interface
As shown in Figure 21, the V.11 protocol is a fully balanced differential interface. The V.11 driver generates a minimum of 2V between nodes A and B when a 100 (min) resistance is present at the load. The V.11 receiver is sensitive to differential signals of 200mV at receiver inputs A' and B'. The V.11 receiver input must comply with the impedance curve of Figure 22 and reject common-mode signals developed across the cable (referenced from C to C' in Figure 21) of up to 7V. The MAX13171E/MAX13173E V.11 mode receivers have a differential threshold between -50mV and -200mV to ensure that the receiver has fail-safe operation (see the Fail-Safe section.) To aid in rejecting system noise, the MAX13171E/MAX13173E V.11 receivers have a typical hysteresis of 15mV. Switch S3 in Figure 23 is open in V.11 mode to disable the V.28 5k termination at the inverting receiver input. Because the control signals are slow (60kbps), 100 termination resistance is generally not required for the MAX13173E. For high-speed data transmission, the V.11 specification recommends terminating the cable at the receiver with a 100 resistor. This resistor, although not required, prevents reflections from corrupting transmitted data. In Figure 23, the MAX13175E is used to terminate the V.11 receiver. Internal to the MAX13175E, S1 is closed and S2 is open to present a 100 minimum differential resistance. The MAX13171E's internal V.28 termination is disabled by opening S3.
MAX13171E/MAX13173E/MAX13175E
GENERATOR
BALANCED INTERCONNECTING CABLE
LOAD CABLE TERMINATION RECEIVER -10V 100 MIN -3V
IZ
+3.25mA
A
A
+3V
VZ +10V
B C
B C
-3.25mA
Figure 21. Typical V.11 Interface
Figure 22. Receiver Input Impedance
A
A R5 55k R1 52
MAX13171E
MAX13175E
R8 5k
R6 11k
RECEIVER
S1 S2 R3 127
S3 + 1.4V R7 S1
R2 52 B B
R4 11k 55k S2 GND
C
Figure 23. V.11 Termination and Internal Resistance Networks
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Multiprotocol, Pin-Selectable Data Interface Chipset MAX13171E/MAX13173E/MAX13175E
V.28 (RS-232) Interface
The V.28 interface is an unbalanced single-ended interface (Figure 18). The V.28 driver generates a minimum of 5V across the 3k load impedance between A' and C'. The V.28 receiver has a single-ended input. The MAX13171E/MAX13173E V.28 mode receivers have a threshold between +0.8V and +2.0V. To aid in rejecting system noise, the MAX13171E/MAX13173E V.28 receivers have a typical hysteresis of 250mV. Switch S3 in Figures 24a and 24b is closed in V.28 mode to enable the 5k V.28 termination at the receiver inputs. load termination networks. The V.35 receiver is sensitive to 200mV differential signals at receiver inputs A' and B'. The V.35 receiver rejects common-mode signals developed across the cable (referenced from C to C') of up to 4V, allowing for error-free reception in noisy environments. In Figure 26, the MAX13175E is used to implement the resistive T-network that is needed to properly terminate the V.35 driver and receiver. Internal to the MAX13175E, S1 and S2 are closed to connect the Tnetwork resistors to the circuit. The V.28 termination resistor (internal to the MAX13171E) is disabled by opening S3 to avoid interference with the T-network impedance. The V.35 specification allows for 4V of ground difference between the V.35 generator and V.35 load. The MAX13174E maintains correct termination impedance over this condition.
V.35 Interface
Figure 25 shows a fully-balanced, differential standard V.35 interface. The generator and the load must both present a 100 10 differential impedance and a 150 15 common-mode impedance as shown by the resistive T-networks in Figure 26. The V.35 driver generates a current output (11mA, typ) that develops an output voltage of 550mV across the generator and
A
A R5 55k R8 5k R6 11k
A
A R5 55k R8 5k R6 11k
MAX13171E MAX13173E
MAX13173E
RECEIVER S3
RECEIVER
S3 + 1.4V R7 11k B B R4 55k S1
C GND
S2
C GND
Figure 24a. V.28 Termination and Internal Resistance Network for Receiver 1, 2, and 3
Figure 24b. V.28 Internal Resistance Network for Receiver 4 and 5
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Multiprotocol, Pin-Selectable Data Interface Chipset MAX13171E/MAX13173E/MAX13175E
GENERATOR BALANCED INTERCONNECTING CABLE A 50 A CABLE TERMINATION 50 LOAD RECEIVER
125
125
50 B C GND B C GND
50
Figure 25. Typical V.35 Interface
A
A R5 55k R1 52
MAX13171E
MAX13175E
R8 5k
R6 11k
RECEIVER
S1 S2 R3 127
S3 + 1.4V
R2 52 B B R4 55k S2 GND
R7 11k S1
C
Figure 26. V.35 Termination and Internal Resistance Networks
DTE/DCE Mode Applications
The MAX13171E/MAX13173E can be hardwired for either DTE or DCE mode in one of two ways: a dedicated DTE or DCE port with an appropriate gender connector, or a port with a connector that can be configured for DTE or DCE operation by rerouting the signals to the MAX13171E and MAX13173E, using a dedicated DTE cable or dedicated DCE cable. The interface mode is selected by logic outputs from the controller or from jumpers to either VL or GND on the mode select inputs.
A dedicated DCE port using a DB-25 female connector is shown in Figure 28. Figure 29 illustrates a dedicated DTE port using a DB-25 male connector. Figure 27 shows an application circuit with one common DB-25 connector that can be configured for either DTE or DCE mode. The configuration requires separate cables for proper signal routing in DTE or DCE operation. Figure 27 illustrates a DCE or DTE controller-selectable interface. The DCE/DTE and INVERT inputs switch the port's mode of operation (Tables 1, 2).
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Multiprotocol, Pin-Selectable Data Interface Chipset MAX13171E/MAX13173E/MAX13175E
VCC C4 4.7F 100pF 100pF 100pF VCC 0.1F VDD MAX13175E DCE/DTE M2 C1 1F VDD C3 4.7F CHARGE PUMP VEE R1A R1B R2A R2B R3A R3B R4A R4B R5A R5B 0.1F R6A R6B C5 4.7F T1OUTA T1OUTB T2OUTA T2OUTB VEE C2 1F 0.1F LATCH M1 M0 VL 0.1F
DTE_TXD/DCE_RXD DTE_SCTE/DCE_RXC
T1IN T2IN T3IN
T1 T2 T3 R1 R2 R3 MAX13171E M0 M1 M2 DCE/DTE
DTE 2 TXD A 14 TXD B 24 SCTE A 11 SCTE B 15 12 17 9 3 16 7
DCE RXD A RXD B RXC A RXC B
DTE_TXC/DCE_TXC DTE_RXC/DCE_SCTE DTE_RXD/DCE_TXD VL 0.1F
R1OUT R2OUT R3OUT
T3OUTA/R1INA T3OUTB/R1INB R2INA R2INB R3INA R3INB
TXC A TXC B
TXC A TXC B
RXC A SCTE A RXC B SCTE B RXD A TXD A RXD B TXD B SG
1
SHIELD
DB-25 CONNECTOR C4 4.7F VCC C1 1F VDD C3 4.7F CHARGE PUMP VEE C5 4.7F T1OUTA DTE_RTS/DCE_CTS DTE_DTR/DCE_DSR T1IN T2IN T3IN DTE_DCD/DCE_DCD R1OUT DTE_DSR/DCE_DTR R2OUT DTE_CTS/DCE_RTS R3OUT DTE_LL/DCE_LL T4IN R4OUT R5OUT/T5IN VL 0.1F MAX13173E M0 M1 M2 DCE/DTE INVERT DCE/DTE M2 M1 M0 INVERT T1 T2 T3 R1 R2 R3 T4 R4 T5 R5 T5OUTA/R5INA T3OUTA/R1INA T3OUTB/R1INB R2INA R2INB R3INA R3INB T4OUTA/R4INA 8 DCD A 10 DCD B 6 DSR A 22 DSR B 5 CTS A 13 CTS B DCD A DCD B DTR A DTR B RTS A RTS B T1OUTB T2OUTA T2OUTB 4 19 20 23 RTS A RTS B DTR A DTR B CTS A CTS B DSR A DSR B C2 1F
Figure 27. Controller-Selectable Multiprotocol DCE/DTE Port with DB-25 Connector
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Multiprotocol, Pin-Selectable Data Interface Chipset MAX13171E/MAX13173E/MAX13175E
VCC C4 4.7F 100pF 100pF 100pF VCC 0.1F VDD MAX13175E DCE/DTE M2 M1 C1 1F VDD C3 4.7F CHARGE PUMP VEE R1A R1B R2A R2B R3A R3B R4A R4B R5A R5B 0.1F R6A R6B C5 4.7F T1OUTA T1OUTB T2OUTA T2OUTB VEE C2 1F 0.1F LATCH M0 VL 0.1F
VL
RXD RXC
T1IN T2IN T3IN
T1 T2 T3 R1 R2 R3 MAX13171E M0 M1 M2 DCE/DTE
DCE 3 RXD A (104) 16 RXD B 17 RXC A (115) 9 RXC B 15 12 24 11 2 14 7
TXC SCTE TXD VL 0.1F
R1OUT R2OUT R3OUT
T3OUTA/R1INA T3OUTB/R1INB R2INA R2INB R3INA R3INB
TXC A (114) TXC B SCTE A (113) SCTE B TXD A (103) TXD B SG
1
SHIELD (101)
NC
C4 4.7F
VCC C1 1F VDD C3 4.7F CHARGE PUMP VEE C5 4.7F T1OUTA 4 19 20 23 C2 1F
DB-25 FEMALE CONNECTOR
CTS DSR
T1IN T2IN T3IN
T1 T2 T3 R1 R2 R3 T4 R4 T5 R5
T1OUTB T2OUTA T2OUTB
CTS A CTS B DSR A DSR B
DCD R1OUT DTR R2OUT RTS R3OUT LL T4IN R4OUT R5OUT/T5IN VL 0.1F
T3OUTA/R1INA T3OUTB/R1INB R2INA R2INB R3INA R3INB T4OUTA/R4INA
8 DCD A (109) 10 DCD B 20 DTR A (108) 23 DTR B 4 RTS A (105) 19 RTS B 18 LL A (141)
T5OUTA/R5INA
NC M2 M1 M0 INVERT
MAX13173E M0 M1 M2 DCE/DTE INVERT
Figure 28. Controller-Selectable DCE Port with DB-25 Connector
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Multiprotocol, Pin-Selectable Data Interface Chipset MAX13171E/MAX13173E/MAX13175E
VCC C4 4.7F 100pF 100pF 100pF VCC 0.1F VDD MAX13175E DCE/DTE M2 C1 1F VDD C3 4.7F CHARGE PUMP VEE R1A R1B R2A R2B R3A R3B R4A R4B R5A R5B 0.1F R6A R6B C5 4.7F T1OUTA T1OUTB T2OUTA T2OUTB VEE C2 1F 0.1F LATCH M1 M0 VL 0.1F
TXD SCTE
T1IN T2IN T3IN
T1 T2 T3 R1 R2 R3 MAX13171E M0 M1 M2 DCE/DTE
DTE 2 TXD A (103) 14 TXD B 24 SCTE A (113) 11 SCTE B 15 12 17 9 3 14 7
TXC RXC RXD VL 0.1F
R1OUT R2OUT R3OUT
T3OUTA/R1INA T3OUTB/R1INB R2INA R2INB R3INA R3INB
TXC A (114) TXC B RXC A (115) RXC B RXD A (104) RXD B SG
1
SHIELD (101)
DB-25 MALE CONNECTOR C4 4.7F VCC C1 1F VDD C3 4.7F CHARGE PUMP VEE C5 4.7F T1OUTA RTS DTR T1IN T2IN T3IN DCD R1OUT DSR R2OUT CTS R3OUT LL T4IN R4OUT R5OUT/T5IN VL 0.1F MAX13173E M0 M1 M2 DCE/DTE INVERT M2 M1 M0 INVERT T1 T2 T3 R1 R2 R3 T4 R4 T5 R5 T5OUTA/R5INA T3OUTA/R1INA T3OUTB/R1INB R2INA R2INB R3INA R3INB T4OUTA/R4INA 8 DCD A (109) 10 DCD B 6 DSR A (107) 22 DSR B 5 CTS A (106) 13 CTS B 18 LL A (141) T1OUTB T2OUTA T2OUTB 4 19 20 23 RTS A (105) RTS B DTR A (108) DTR B C2 1F
Figure 29. Controller-Selectable Multiprotocol DTE Port with DB-25 Connector
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Multiprotocol, Pin-Selectable Data Interface Chipset
Complete Multiprotocol X.21 Interface
A complete DTE-to-DCE interface operating in X.21 mode is shown in Figure 30. The MAX13171E is used to generate the clock and data signals, and the MAX13173E generates the control signals and local loopback (LL). The MAX13175E is used to terminate the clock and data signals to support the V.11 protocol for cable termination. The control signals do not need external termination. extra protection against static electricity. Maxim's engineers have developed state-of-the-art structures to protect these pins against ESD of 15kV without damage. The ESD structures withstand high ESD in all states: normal operation, shutdown, and powered down. After an ESD event, the MAX13171E/MAX13173E/MAX13175E keep working without latchup or damage. ESD protection can be tested in various ways. The Electrical Characteristics table shows the various limits for each device and they are characterized for protection to the following methods: * Human Body Model * Contact Method specified in IEC 61000-4-2 * Air-Gap Discharge Method specified in IEC 61000-4-2
DCE
MAX13175E MAX13175E MAX13171E
MAX13171E/MAX13173E/MAX13175E
ESD Protection
ESD-protection structures are incorporated on all pins to protect against electrostatic discharges encountered during handling and assembly. The driver outputs and receiver inputs of the MAX13171E/MAX13173E have
DTE SERIAL CONTROLLER TXD SCTE
MAX13171E
SERIAL CONTROLLER TXD SCTE
T1 T2 T3
TXD SCTE
104 104
R3 R2 R1
TXC RXC
R3 R2
104 104
TXC RXC RXD
T1 T2
TXC RXC
RXD
R1
104
T3
RXD
MAX13173E
MAX13173E
RTS DTR
T1 T2 T3
RTS DTR
R3 R2 R1
RTS DTR
DCD DSR CTS LL
R1 R2 R3 D4 T4
DCD DSR CTS LL
T3 T2 T1 R4 T4
DCD DSR CTS LL
Figure 30. DCE-to-DTE X.21 Interface
______________________________________________________________________________________ 35
Multiprotocol, Pin-Selectable Data Interface Chipset MAX13171E/MAX13173E/MAX13175E
ESD Test Conditions ESD performance depends on a variety of conditions. Contact Maxim for a reliability report that documents test setup, test methodology, and test results. Human Body Model Figure 31a shows the Human Body Model, and Figure 31b shows the current waveform it generates when discharged into a low impedance. This model consists of a 100pF capacitor charged to the ESD voltage of interest, which is then discharged into the test device through a 1.5k resistor. IEC 61000-4-2 The IEC 61000-4-2 standard covers ESD testing and performance of finished equipment. However, it does not specifically refer to integrated circuits. The MAX13171E/MAX13173E/MAX13175E help equipment designs to meet IEC 61000-4-2, without the need for additional ESD-protection components. The major difference between tests done using the Human Body Model and IEC 61000-4-2 is higher peak current in IEC 61000-4-2 because series resistance is lower in the IEC 61000-4-2 model. Figure 31c shows the IEC 61000-4-2 model, and Figure 31d shows the current waveform for the IEC 61000-4-2 ESD Contact Discharge test.
RC 1M CHARGE-CURRENT LIMIT RESISTOR HIGHVOLTAGE DC SOURCE
RD 1500 DISCHARGE RESISTANCE DEVICE UNDER TEST
RC 50M TO 100M CHARGE-CURRENT LIMIT RESISTOR HIGHVOLTAGE DC SOURCE
RD 330 DISCHARGE RESISTANCE DEVICE UNDER TEST
Cs 100pF
STORAGE CAPACITOR
Cs 150pF
STORAGE CAPACITOR
Figure 31a. Human Body ESD Test Model
Figure 31c. ICE 61000-4-2 ESD Test Model
IP 100% 90% AMPS 36.8% 10% 0 0 tRL TIME
Ir
PEAK-TO-PEAK RINGING (NOT DRAWN TO SCALE) IPEAK
I 100% 90%
10% tr = 0.7ns TO 1ns 30ns 60ns t
tDL CURRENT WAVEFORM
Figure 31b. Human Body Current Waveform
Figure 31d. IEC 61000-4-2 ESD Generator Current Waveform
36
______________________________________________________________________________________
Multiprotocol, Pin-Selectable Data Interface Chipset
Pin Configurations
TOP VIEW
T3OUTA/R1INA T3OUTB/R1INB T1OUTA T1OUTB T2OUTA T2OUTB
MAX13171E/MAX13173E/MAX13175E
R2INA 21
31 VEE 32 C2- 33 C2+ 34 GND 35 C1- 36 C1+ 37 VDD 38
30
29
28
27
26
25
24
23
22
20 19 GND 18 R3INA 17 R3INB
MAX13171E
R2INB 16 VCC 15 DCE/DTE 14 M2 13 M1 12 VL 20 19 R3INB 18 GND 17 T4OUTA/R4INA R3INA 16 INVERT 15 DCE/DTE 14 M2 13 M1 12 M0
GND
GND
N.C.
N.C.
*EP
+
1 N.C. 2 N.C. 3 VCC 4 T1IN 5 T2IN 6 N.C. 7 T3IN 8 R1OUT 9 R2OUT 10 R3OUT R2INA 22 10 T4IN 11 M0 21 *EP 11 R4OUT R2INB
TQFN
*CONNECT EXPOSED PAD TO VEE.
T5OUTA/R5INA
T3OUTA/R1INA 24 8 R3OUT
31 VEE 32 C2- 33 C2+ 34 GND 35 C1- 36 C1+ 37 VDD 38
30
29
28
27
26
25
23
MAX13173E
+
1 T1IN 2 VCC 3 T2IN 4 T3IN 5 VL 6 R1OUT 7 R2OUT 9 R5OUT/T5IN
TQFN
*CONNECT EXPOSED PAD TO VEE.
______________________________________________________________________________________
T3OUTB/R1INB
T1OUTA
T1OUTB
T2OUTA
T2OUTB
GND
GND
37
Multiprotocol, Pin-Selectable Data Interface Chipset MAX13171E/MAX13173E/MAX13175E
Pin Configurations (continued)
TOP VIEW
R6B R6B R6A R6A R5A R5A R5B R5B R4A R4A R4B 21 R4B 20 19 VCC 18 GND 17 VDD 16 VEE 15 VL *EP 14 R3C 13 GND 2 R1A 3 R1A 4 R2A 5 R2A 6 R2B 7 R2B 8 R2C 9 R3A 10 R3A 11 R3B 12 R3B
31 DCE/DTE 32 LATCH 33 M2 34 M1 35 M0 36 R1C 37 R1B 38
30
29
28
27
26
25
24
23
22
MAX13175E
+
1 R1B
TQFN
*CONNECT EXPOSED PAD TO VEE
Chip Information
PROCESS: BiCMOS
PACKAGE TYPE 38 TQFN-EP
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE CODE T3857-1 DOCUMENT NO. 21-0172
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
38 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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